VHDL - An Introduction

VHDL is VHSIC (Very High Speed Integrated Circuit) Hardware Descriptive Language. It is a programming language that has been designed and optimized for describing the behavior of digital circuits and systems. It can be used to describe the behavior, structure and implementation of electronic systems. It is a design tool that aims to manage the complexity of design through the use of logic synthesis tools to generate automatically a hardware structure that meets the specifications.

VHDL is recognized as a standard HDL by the IEEE (IEEE Standard 1164 and by the United States Department of Defense (MIL-STD-454L). This standard defines a standard package (a VHDL feature that allows commonly used declarations to be collected into an external library) containing definitions for a standard 9-valued data type. IEEE 1164 package is often referred to as the standard logic package.

Applications of VHDL

• Development of a formal model of system behavior
• VHDL models can serve as system documentation
• Digital Circuits captured using VHDL can be archived for later modification and reuse

VHDL is a Hardware Descriptive Language. It has the following features:

• Digital circuits captured using VHDL can be easily simulated
• They can be synthesized into multiple technologies
• They can be archived for later modification and reuse

Advantages of using VHDL

• Allows description of structure of design (how it is decomposed into sub designs, how they are connected)
• Allows Simulation

Limitations of VHDL

• Analog Simulation possible. No synthesis possible
• Mixed signal simulation has to deal with the problem of synchronizing analog and digital simulation.

VHDL Terms

These are the basic VHDL building blocks that are used in almost every description, along with some terms that are redefined in HDL to mean something to the average designer.

• Entity - All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lower-level descriptions contained in it. These lower-level descriptions will be lower-level entities contained in the top-level entity description.
• Architecture - All entities that can be simulated have an architecture description. The architecture describes the behaviour of the entity. A single entity can have multiple architectures. One architecture may be behavioural while the other might be a structural description of the design.

Difference between an entity and an architecture

• Process - A process is the basic unit of execution in VHDL All operations that are performed in a simulation of a VHDL description are broken down into single or multiple processes.

Levels of Abstraction

VHDL can be used to describe electronic hardware at many different levels of abstraction. When considering the application of VHDL to FPGA design, it is helpful to identify and understand the three levels of abstractions viz. algorithm, register transfer level (RTL) and gate level. Algorithms are unsynthesizable, RTL is the input to the synthesis, gate level is the output from the synthesis.

• Algorithm - A pure algorithm has a set of instructions that are executed in sequence to perform some task
• RTL - It is characterized by a style that specifies all the registers in a design and all the combinational logic between. The registers are all connected to a clock signal. The combinational logic is described by logical equations, sequential control statements (CASE, IF then ELSE, etc., or through concurrent statements. They are used for synchronous designs and describe the clock by clock behaviour of the design. The synthesis tools available today convert RTL descriptions to gate level netlists
• Gate Level - This level of abstraction often specifies how the hardware does implement a design. This is generally too low a level for describing hardware and is rarely used.